Power Considerations in Phased Logic Gate Design MSU Tech Report MSSU-COE-ERC-01-03

Phased Logic (PL) is a synthesis and mapping methodology that translates a standard synchronous gate-level netlist to a non-clocked netlist of special gates called phased logic gates [1][2][3]. In this paper the implementation of PL gates and the switched capacitance of phased logic systems is discussed. An analysis of the dynamic power consumption of a phased logic system reveals a major deficiency in the original programmable LUT-based design [2], leading to an alternate phased logic gate design. Switched capacitance comparisons of designs using the new phased logic gate versus clocked FPGA implementations provide insights to PL gate design requirements and the type of applications best suited for phased logic implementation.